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HCF4527B
BCD RATE MULTIPLEXER
s s s
s
s s
s s
CASCADABLE IN MULTIPLES OF 4-BITS SET TO 9 INPUT AND 9 DETECT OUTPUT QUIESCENT CURRENT SPECIFIED UP TO 20V STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES"
DIP
ORDER CODES
PACKAGE DIP TUBE HCF4527BEY T&R
DESCRIPTION HCF4527B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP package. This device is a low power 4-bit digital rate multiplier that provides an output pulse rate which is the clock input pulse rate multiplied by 1/10 times the BCD input. For example, when the BCD
input is 8, there will be 8 output pulses for every 10 input pulses. This device may be used to perform arithmetic operations (add, subtract, divide, raise to a power), solve algebraic and differential equations, generate natural logarithms and trigonometric functions, A/D and D/A conversion, and frequency division.
PIN CONNECTION
October 2002
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HCF4527B
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 14, 15, 2, 3 10 12 5, 6 9 11 4 13 7 1 8 16 SYMBOL A, B, C, D STROBE CASCADE OUT, OUT CLOCK INHIBIT IN SET T0 "9" CLEAR INHIBIT OUT "9" OUT VSS VDD NAME AND FUNCTION BCD Rate Select Inputs Strobe Input Cascade Rate Outputs Clock Input Inhibit Input (Carry) Set Input Clear Input Inhibit Out (Carry) Output Negative Supply Voltage Positive Supply Voltage
FUNCTIONAL DIAGRAM
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HCF4527B
TRUTH TABLE
INPUTS Number of Pulses or Logic Level D L L L L L L L L H H H H H H H H X X X H L X C L L L L H H H H L L L L H H H H X X X X X X B L L H H L L H H L L H H L L H H X X X X X X A L H L H L H L H L H L H L H L H X X X X X X CLK 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 INH IN L L L L L L L L L L L L L L L H L L L L L L STR L L L L L L L L L L L L L L L L H L L L L L CAS L L L L L L L L L L L L L L L L L L H L L L CLR L L L L L L L L L L L L L L L L L L L H H L SET L L L L L L L L L L L L L L L L L L L L L H OUTPUTS Number of Pulses or Output Logic Level OUT L 1 2 3 4 5 6 7 8 9 8 9 8 9 8 9 ** L H 10 L L OUT H 1 2 3 4 5 6 7 8 9 8 9 8 9 8 9 ** H * 10 H H INH OUT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 H 1 1 H H L "9" OUT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ** 1 1 L L H
X : Don't Care ** : Depends on internal state of counter. * : Output same as the first 16 lines of this truth table (depending on value of A, B, C, D)
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HCF4527B
LOGIC DIAGRAM
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HCF4527B
TIMING CHART
ABSOLUTE MAXIMUM RATINGS
Symbol VDD VI II PD Top Tstg Supply Voltage DC Input Voltage DC Input Current Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature Storage Temperature Parameter Value -0.5 to +22 -0.5 to VDD + 0.5 10 200 100 -55 to +125 -65 to +150 Unit V V mA mW mW C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage.
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HCF4527B
RECOMMENDED OPERATING CONDITIONS
Symbol VDD VI Top Supply Voltage Input Voltage Operating Temperature Parameter Value 3 to 20 0 to VDD -55 to 125 Unit V V C
DC SPECIFICATIONS
Test Condition Symbol Parameter VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 0.4 0.5 1.5 VO (V) |IO| VDD (A) (V) 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 5 10 15 18 TA = 25C Min. Typ. 0.04 0.04 0.04 0.08 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 -1.36 -0.44 -1.1 -3.0 1.74 4.42 11.56 0.44 1.1 3.0 -3.2 -1 -2.6 -6.8 4 10.4 27.2 1 2.6 6.8 10-5 5 -1.1 -0.36 -0.9 -2.4 1.43 3.74 9.52 0.36 0.9 2.4 3.5 7 11 1.5 3 4 -1.1 -0.36 -0.9 -2.4 1.43 3.74 9.52 0.36 0.9 2.4 Max. 5 10 20 100 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 Value -40 to 85C Min. Max. 150 300 600 3000 4.95 9.95 14.95 0.05 0.05 0.05 -55 to 125C Min. Max. 150 300 600 3000 Unit
IL
Quiescent Current
A
VOH
High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage Output Drive Current (Source) Q, Q, Q' CLD Output Sink Current Q Output Sink Current Q, Q', CLD Input Leakage Current Input Capacitance
VOL
VIH
VIL
IOH
IOL
IOL
0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/5 0/10 0/15 0/18
<1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1
V
V
V
V
mA
mA
mA
II
Any Input Any Input
0.1
7.5
1
1
A
pF
CI
The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
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HCF4527B
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25C, CL = 50pF, RL = 200K, tr = tf = 20 ns)
Test Condition Symbol Parameter VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 Min. Value (*) Typ. 110 55 45 150 75 60 320 145 100 250 100 75 380 175 130 300 125 90 90 45 35 130 60 45 330 150 110 100 50 40 2.4 5 7 165 85 50 Max. 220 110 90 300 150 120 640 290 200 500 200 150 760 550 260 600 250 180 180 90 70 260 120 90 660 300 220 200 100 80 ns Unit
tPLH, tPHL Propagation Delay Time : Clock to Output tPLH, tPHL Propagation Delay Time : Clock or Strobe to Output tPLH Propagation Delay Time : Clock to Inhibit Output Propagation Delay Time : Clock to Inhibit Output
ns
ns
tPHL
ns
tPLH, tPHL Propagation Delay Time : Clear to Output tPLH, tPHL Propagation Delay Time : Clock to "9" or "1" Q Output tPLH, tPHL Propagation Delay Time : Cascade to Output tPLH, tPHL Propagation Delay Time : Inhibit Input to Inhibit Output tPLH, tPHL Propagation Delay Time : Set to Output tTHL, tTLH Transition Time
ns
ns
ns
ns
ns
ns
fCL
Maximum Clock Frequency Clock Pulse Width
tW
1.2 2.5 3.5 330 170 100
MHz
ns 15 15 15
tr, tf
Clock Rise or Fall Time
s
tW
Set or Clear Pulse Width
tsetup
Inhibit Input Setup Time
160 90 60 100 40 20
80 45 30 50 20 10
ns
ns
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HCF4527B
Test Condition Symbol tR Parameter Inhibit Input Removal Time VDD (V) 5 10 15 5 10 15 5 10 15 Min. 240 130 110 150 80 50 60 40 30
Value (*) Typ. 120 65 55 75 40 25 30 20 15 Max.
Unit
ns
tR
Set Removal Time
ns
tR
Clear Removal Time
ns
(*) Typical temperature coefficient for all VDD value is 0.3 %/C.
APPLICATION NOTE : For fractional multipliers with more than one digit, HCF4527B may be cascaded in two different modes: The ADD mode and the MULTIPLY mode (see figure 1 and 2). When two units are cascaded in ADD mode and programmed to 9 and 4 respectively, the more significant unit will have 9 output pulses for every 10 input pulses and the other will have 4 output pulses for every 100 input pulses for a total of : 9 4 94 + = 10 100 100
In the multiply mode, the fraction programmed into the first rate multiplier is multiplied by the fraction programmed into the second one : If N1 = 9 and N 2 =4 4 fOUT2 = fOUT1 10 9 fOUT1 = fCLOCK 10 4 9 36 fOUT2 = x ( fCLOCK ) = fCLOCK 10 10 100 Therefore 36 output pulses for every 100 clock input pulses
Two HCF4527B Cascaded in the ADD mode with a Preset Number
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HCF4527B
Two HCF4527B Cascaded in the MULTIPLY Mode with a Preset Number
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200K RT = ZOUT of pulse generator (typically 50)
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HCF4527B
WAVEFORM : PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle)
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HCF4527B
Plastic DIP-16 (0.25) MECHANICAL DATA
mm. DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 TYP. MAX. inch
P001C
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HCF4527B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com
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